Field
Embodiments described herein relates to a nonvolatile semiconductor memory device configured with nonvolatile memory cells that are electrically rewritable.
Description of the Related Art
NAND type flash memory is known as nonvolatile semiconductor memory device that is electrically rewritable and suitable for high integration. In NAND type flash memory, a plurality of memory cells are connected in series in a way that the source diffused layer of one memory cell is shared as the drain diffused layer of its adjoining memory cell, thereby forming a NAND cell unit. Both ends of the NAND cell unit are connected to a bit line and a source line respectively via select gate transistors. Such a NAND cell unit configuration enables large-capacity storage with a smaller unit cell area than that of a NOR type memory.
A memory cell of a NAND type flash memory includes a charge accumulation layer (floating gate electrode) provided above a semiconductor substrate via a tunnel insulating film and a control gate electrode stacked above the floating gate electrode via an inter-gate insulating film, and stores data in a nonvolatile manner in accordance with the charge accumulation state of the floating gate electrode. For example, a memory cell executes binary data storage by defining, for example, a high threshold voltage state in which electrons are into the floating gate electrode as data “0”, and defining a low threshold voltage state in which electrons in the floating gate electrode are discharged as data “1”. Recently, multi-value storage of four-value, eight-value, and so on is also undertaken by subdividing a threshold voltage distribution for writing.
A data writing operation of a NAND type flash memory is executed on a page basis. A page is configured by memory cells arranged along a selected word line. Specifically, a writing operation is executed as an operation of supplying a writing voltage to a selected word line and injecting electrons into the floating gate electrode from a cell channel by the effect of FN tunneling. In this case, the potential of the cell channel is controlled in accordance with data “0” or “1” that is to be written.
That is, when data “0” is to be written, a voltage Vss is supplied to the bit line and transferred to the channel of the selected memory cell via a select gate transistor which is conductive. At this time, in the selected memory cell, a high electrical field is applied between the floating gate electrode and the channel to cause electrons to be injected into the floating gate electrode. On the other hand, when data “1” is to be written (i.e., in the case of non-writing), a supply voltage Vdd is supplied to the bit line to charge the cell channel up to a voltage Vdd−Vth (where Vth is the threshold voltage of the select gate transistor), after which the select gate transistor becomes non-conductive state to turn the cell channel into a floating state. At this time, the potential of the cell channel rises due to the effect of capacitance coupling with the word line, thereby inhibiting electrons from being injected into the floating gate electrode.
Recently, as the minimum feature size has become increasingly smaller, the effect caused by capacitance coupling between the floating gate electrodes of adjoining memory cells (inter-cell interference), etc. has become more significant. This effect might cause undesirable dispersion of the threshold voltages of memory cells (writing error and erase error). Particularly, when a memory cell at the end of the NAND cell unit is directly connected to a select gate transistor, there may occur dispersion between the memory cell at the end of the NAND cell unit and the other memory cells in regard to their operation characteristic, increasing the possibility of erroneous writing and erase error. An effective measure for this problem is a method of providing a dummy cell that is not used for data storage at a location adjoining the select gate transistor.
Further, a method of executing a so-called soft program operation is known for solving an over-erased state of the memory cells subsequent to simultaneous erasing. The soft program operation is important for preventing a change of data due to capacitance coupling between the floating gate electrodes of adjoining memory cells. Especially, this operation is critical as a countermeasure technique against writing error in case of shrinking of a NAND type flash memory.
In a nonvolatile semiconductor memory such as a NAND type flash memory, etc., it is preferred to suppress dispersion of the threshold voltages of the nonvolatile memory cells before an erasing operation is executed. Hence, it is proposed that a weak writing operation called pre-program operation be executed before an erasing operation is executed.